# //  ModelSim SE 10.1 Dec  5 2011 Linux 2.6.18-274.17.1.el5
# //
# //  Copyright 1991-2011 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
#  
vlib work
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/Johnson_count.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module Johnson_count
# 
# Top level modules:
# 	Johnson_count
vsim -voptargs=+acc work.Johnson_count
# vsim -voptargs=+acc work.Johnson_count 
# ** Note: (vsim-3812) Design is being optimized...
# Loading work.Johnson_count(fast)
add wave -position anchor  \
sim:/Johnson_count/clk
add wave -position anchor  \
sim:/Johnson_count/r
add wave -position anchor  \
sim:/Johnson_count/out
add wave  \
sim:/Johnson_count/clk
force -freeze sim:/Johnson_count/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/Johnson_count/r 0 0
run
run
run
force -freeze sim:/Johnson_count/r 1 0
run
force -freeze sim:/Johnson_count/r 0 0
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
vsim -voptargs=+acc work.Johnson_count
# vsim -voptargs=+acc work.Johnson_count 
# Loading work.Johnson_count(fast)
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module Johnson_count_1
# 
# Top level modules:
# 	Johnson_count_1
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module Johnson_count_1
# 
# Top level modules:
# 	Johnson_count_1
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module Johnson_count_1
# 
# Top level modules:
# 	Johnson_count_1
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module Johnson_count_1
# 
# Top level modules:
# 	Johnson_count_1
vsim -voptargs=+acc work.Johnson_count_1
# vsim -voptargs=+acc work.Johnson_count_1 
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(8): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(9): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(10): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(11): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(12): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(13): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(14): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(15): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(16): Module 'INVX0' is not defined.
# Optimization failed
# Error loading design
vsim -voptargs=+acc work.Johnson_count_1
# vsim -voptargs=+acc work.Johnson_count_1 
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(8): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(9): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(10): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(11): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(12): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(13): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(14): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(15): Module 'DFFARX1' is not defined.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/work/johnson.v(16): Module 'INVX0' is not defined.
# Optimization failed
# Error loading design
vsim -voptargs=+acc work.Johnson_count
# vsim -voptargs=+acc work.Johnson_count 
# Loading work.Johnson_count(fast)
add wave -position anchor  \
sim:/Johnson_count/size \
sim:/Johnson_count/clk \
sim:/Johnson_count/r \
sim:/Johnson_count/out
force -freeze sim:/Johnson_count/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/Johnson_count/r 1 0
run
run
run
run
force -freeze sim:/Johnson_count/r 0 0
run
run
run
run
run
run
run
run
run
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/decoder.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module decoder_using_assign
# 
# Top level modules:
# 	decoder_using_assign
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/decoder.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module decoder_using_assign
# 
# Top level modules:
# 	decoder_using_assign
vsim -voptargs=+acc work.decoder_using_assign
# vsim -voptargs=+acc work.decoder_using_assign 
# ** Note: (vsim-3812) Design is being optimized...
# Loading work.decoder_using_assign(fast)
add wave -position anchor  \
sim:/decoder_using_assign/binary_in \
sim:/decoder_using_assign/enable \
sim:/decoder_using_assign/decoder_out
force -freeze sim:/decoder_using_assign/binary_in 0000 0
force -freeze sim:/decoder_using_assign/enable 0 0
run
run
force -freeze sim:/decoder_using_assign/enable 1 0
run
run
force -freeze sim:/decoder_using_assign/binary_in 1111 0
run
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/example/example.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module example
# 
# Top level modules:
# 	example
vsim -voptargs=+acc work.example
# vsim -voptargs=+acc work.example 
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/example/example.v(16): Module 'incrementer' is not defined.
# Optimization failed
# Error loading design
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/example/example.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module example
# 
# Top level modules:
# 	example
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/example/incrementer.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module incrementer
# 
# Top level modules:
# 	incrementer
vsim -voptargs=+acc work.example
# vsim -voptargs=+acc work.example 
# ** Note: (vsim-3812) Design is being optimized...
# Loading work.example(fast)
# Loading work.incrementer(fast)
add wave -position anchor  \
sim:/example/clk \
sim:/example/rst \
sim:/example/in1 \
sim:/example/in2 \
sim:/example/out1 \
sim:/example/out2 \
sim:/example/out3
force -freeze sim:/example/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/example/rst 1 0
force -freeze sim:/example/in1 0101 0
force -freeze sim:/example/in2 1011 0
run
run
force -freeze sim:/example/rst 0 0
run
run
force -freeze sim:/example/in1 0100 0
run
run
force -freeze sim:/example/in2 0000 0
run
force -freeze sim:/example/in1 1011 0
run
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/example/incrementer.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module incrementer
# 
# Top level modules:
# 	incrementer
vsim -voptargs=+acc work.incrementer
# vsim -voptargs=+acc work.incrementer 
# ** Note: (vsim-3812) Design is being optimized...
# Loading work.incrementer(fast)
add wave -position anchor  \
sim:/incrementer/in_val \
sim:/incrementer/out_val
force -freeze sim:/incrementer/in_val 1111 0
run
run
force -freeze sim:/incrementer/in_val 0000 0
run
run
run
force -freeze sim:/incrementer/in_val 1010 0
run
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module incrementer
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(17): A begin/end block was found with an empty body.  This is permitted in SystemVerilog, but not permitted in Verilog.  Please look for any stray semicolons.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(22): A begin/end block was found with an empty body.  This is permitted in SystemVerilog, but not permitted in Verilog.  Please look for any stray semicolons.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(31): A begin/end block was found with an empty body.  This is permitted in SystemVerilog, but not permitted in Verilog.  Please look for any stray semicolons.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(36): A begin/end block was found with an empty body.  This is permitted in SystemVerilog, but not permitted in Verilog.  Please look for any stray semicolons.
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module incrementer
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(16): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(17): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(21): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(22): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(30): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(31): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(35): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(36): (vlog-2110) Illegal reference to net "BLB".
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module incrementer
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(18): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(19): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(23): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(24): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(32): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(33): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(37): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(38): (vlog-2110) Illegal reference to net "BLB".
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(18): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(19): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(23): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(24): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(32): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(33): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(37): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(38): (vlog-2110) Illegal reference to net "BLB".
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(18): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(19): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(23): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(24): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(32): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(33): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(37): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(38): (vlog-2110) Illegal reference to net "BLB".
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(18): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(19): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(23): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(24): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(32): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(33): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(37): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(38): (vlog-2110) Illegal reference to net "BLB".
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/decoder.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module decoder_using_assign
# 
# Top level modules:
# 	decoder_using_assign
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(18): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(19): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(23): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(24): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(32): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(33): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(37): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(38): (vlog-2110) Illegal reference to net "BLB".
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(18): LHS in procedural continuous assignment may not be a net: BL.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(19): LHS in procedural continuous assignment may not be a net: BLB.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(23): LHS in procedural continuous assignment may not be a net: BL.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(24): LHS in procedural continuous assignment may not be a net: BLB.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(32): LHS in procedural continuous assignment may not be a net: BL.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(33): LHS in procedural continuous assignment may not be a net: BLB.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(37): LHS in procedural continuous assignment may not be a net: BL.
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(38): LHS in procedural continuous assignment may not be a net: BLB.
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(16): The generate if condition must be a constant expression.
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(18): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(19): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(23): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(24): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(32): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(33): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(37): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(38): (vlog-2110) Illegal reference to net "BLB".
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(18): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(19): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(23): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(24): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(32): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(33): (vlog-2110) Illegal reference to net "BLB".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(37): (vlog-2110) Illegal reference to net "BL".
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(38): (vlog-2110) Illegal reference to net "BLB".
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# 
# Top level modules:
# 	timing
vsim -voptargs=+acc work.timing
# vsim -voptargs=+acc work.timing 
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(13): Module 'decoder' is not defined.
# Optimization failed
# Error loading design
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/decoder.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module decoder_using_assign
# 
# Top level modules:
# 	decoder_using_assign
vsim -voptargs=+acc work.timing
# vsim -voptargs=+acc work.timing 
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(13): Module 'decoder' is not defined.
# Optimization failed
# Error loading design
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/decoder.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module decoder_using_assign
# 
# Top level modules:
# 	decoder_using_assign
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# 
# Top level modules:
# 	timing
vsim -voptargs=+acc work.timing
# vsim -voptargs=+acc work.timing 
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(13): Module 'decoder' is not defined.
# Optimization failed
# Error loading design
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# 
# Top level modules:
# 	timing
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/decoder.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module decoder_using_assign
# 
# Top level modules:
# 	decoder_using_assign
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# 
# Top level modules:
# 	timing
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/decoder.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module decoder_using_assign
# 
# Top level modules:
# 	decoder_using_assign
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# 
# Top level modules:
# 	timing
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/decoder.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module decoder_using_assign
# 
# Top level modules:
# 	decoder_using_assign
vsim -voptargs=+acc work.timing
# vsim -voptargs=+acc work.timing 
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(13): Module 'decoder' is not defined.
# Optimization failed
# Error loading design
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/decoder.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module decoder_using_assign
# 
# Top level modules:
# 	decoder_using_assign
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/decoder.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module decoder
# 
# Top level modules:
# 	decoder
vsim -voptargs=+acc work.timing
# vsim -voptargs=+acc work.timing 
# ** Note: (vsim-3812) Design is being optimized...
# Loading work.timing(fast)
# Loading work.decoder(fast)
add wave -position anchor  \
sim:/timing/adr \
sim:/timing/data_in \
sim:/timing/read \
sim:/timing/enable \
sim:/timing/clk \
sim:/timing/BL \
sim:/timing/BLB \
sim:/timing/WL \
sim:/timing/clk_en
force -freeze sim:/timing/adr 0101 0
force -freeze sim:/timing/data_in 1010101010101010 0
force -freeze sim:/timing/data_in 1010101010101010 0
force -freeze sim:/timing/read 0 0
force -freeze sim:/timing/enable 0 0
force -freeze sim:/timing/clk 1 0, 0 {50 ns} -r 100
run
run
run
force -freeze sim:/timing/enable 1 0
run
run
run
force -freeze sim:/timing/clk 0 0, 1 {50 ns} -r 100
restart
# Loading work.timing(fast)
# Loading work.decoder(fast)
run
force -freeze sim:/timing/adr 1011 0
force -freeze sim:/timing/data_in 1100110011001100 0
force -freeze sim:/timing/read 0 0
force -freeze sim:/timing/enable 0 0
force -freeze sim:/timing/clk 0 0, 1 {50 ns} -r 100
run
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# 
# Top level modules:
# 	timing
restart
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading work.timing(fast)
# Loading work.decoder(fast)
vsim -voptargs=+acc work.timing
# vsim -voptargs=+acc work.timing 
# Loading work.timing(fast)
# Loading work.decoder(fast)
add wave -position anchor  \
sim:/timing/adr \
sim:/timing/data_in \
sim:/timing/read \
sim:/timing/enable \
sim:/timing/clk \
sim:/timing/BL \
sim:/timing/BLB \
sim:/timing/WL \
sim:/timing/clk_en
force -freeze sim:/timing/adr 0101 0
force -freeze sim:/timing/data_in 0101010101010101 0
force -freeze sim:/timing/read 0 0
force -freeze sim:/timing/enable 0 0
force -freeze sim:/timing/clk 0 0, 1 {50 ns} -r 100
run
run
run
force -freeze sim:/timing/enable 1 0
run
run
run
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# 
# Top level modules:
# 	timing
vsim -voptargs=+acc work.timing
# vsim -voptargs=+acc work.timing 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading work.timing(fast)
# Loading work.decoder(fast)
add wave -position anchor  \
sim:/timing/adr \
sim:/timing/data_in \
sim:/timing/read \
sim:/timing/enable \
sim:/timing/clk \
sim:/timing/BL \
sim:/timing/BLB \
sim:/timing/WL \
sim:/timing/clk_en
force -freeze sim:/timing/adr 0011 0
force -freeze sim:/timing/data_in 1010101010101010 0
force -freeze sim:/timing/read 0 0
force -freeze sim:/timing/enable 0 0
force -freeze sim:/timing/clk 0 0, 1 {50 ns} -r 100
run
run
force -freeze sim:/timing/enable 1 0
run
run
force -freeze sim:/timing/read 1 0
run
run
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# ** Warning: (vlog-6) -- Waiting for lock by "jmb9zw@class4.ee.Virginia.EDU, pid = 19249". Lockfile is "/net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/work/_lock".
# -- Compiling module timing
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(29): near "posedge": syntax error, unexpected posedge
# -- Compiling module timing
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(29): near "posedge": syntax error, unexpected posedge
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# 
# Top level modules:
# 	timing
vsim -voptargs=+acc work.timing
# vsim -voptargs=+acc work.timing 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading work.timing(fast)
# Loading work.decoder(fast)
add wave -position anchor  \
sim:/timing/adr \
sim:/timing/data_in \
sim:/timing/read \
sim:/timing/enable \
sim:/timing/clk \
sim:/timing/BL \
sim:/timing/BLB \
sim:/timing/WL \
sim:/timing/clk_en
force -freeze sim:/timing/adr 1010 0
force -freeze sim:/timing/data_in 1010101010101010 0
force -freeze sim:/timing/read 0 0
force -freeze sim:/timing/enable 0 0
force -freeze sim:/timing/clk 0 0, 1 {50 ns} -r 100
run
run
force -freeze sim:/timing/enable 1 0
run
run
force -freeze sim:/timing/read 1 0
run
run
force -freeze sim:/timing/read 0 0
run
run
run
force -freeze sim:/timing/read 1 0
run
run
run
run
run
run
run
run
run
run
run
run
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# 
# Top level modules:
# 	timing
vsim -voptargs=+acc work.timing
# vsim -voptargs=+acc work.timing 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading work.timing(fast)
# Loading work.decoder(fast)
add wave -position anchor  \
sim:/timing/adr \
sim:/timing/data_in \
sim:/timing/read \
sim:/timing/enable \
sim:/timing/clk \
sim:/timing/BL \
sim:/timing/BLB \
sim:/timing/WL \
sim:/timing/clk_en
force -freeze sim:/timing/adr 1111 0
force -freeze sim:/timing/data_in 1010101010101010 0
force -freeze sim:/timing/read 1 0
force -freeze sim:/timing/enable 1 0
force -freeze sim:/timing/clk 1 0, 0 {50 ns} -r 100
run
run
run
run
run
run
run
run
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# 
# Top level modules:
# 	timing
vsim -voptargs=+acc work.timing
# vsim -voptargs=+acc work.timing 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading work.timing(fast)
# Loading work.decoder(fast)
add wave -position anchor  \
sim:/timing/adr \
sim:/timing/data_in \
sim:/timing/read \
sim:/timing/enable \
sim:/timing/clk \
sim:/timing/BL \
sim:/timing/BLB \
sim:/timing/WL \
sim:/timing/clk_en
force -freeze sim:/timing/adr 1010 0
force -freeze sim:/timing/data_in 1100110011001100 0
force -freeze sim:/timing/read 0 0
force -freeze sim:/timing/enable 0 0
force -freeze sim:/timing/clk 1 0, 0 {50 ns} -r 100
run
run
force -freeze sim:/timing/enable 1 0
run
run
run
force -freeze sim:/timing/read 1 0
run
run
run
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# 
# Top level modules:
# 	timing
vsim -voptargs=+acc work.timing
# vsim -voptargs=+acc work.timing 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading work.timing(fast)
# Loading work.decoder(fast)
# Load canceled
add wave -position anchor  \
sim:/timing/adr \
sim:/timing/data_in \
sim:/timing/read \
sim:/timing/enable \
sim:/timing/clk \
sim:/timing/BL \
sim:/timing/BLB \
sim:/timing/WL \
sim:/timing/clk_en
force -freeze sim:/timing/read 1 0
force -freeze sim:/timing/enable 0 0
force -freeze sim:/timing/clk 1 0, 0 {50 ns} -r 100
force -freeze sim:/timing/data_in 1110001010101010 0
force -freeze sim:/timing/adr 1111 0
run
run
run
force -freeze sim:/timing/enable 1 0
run
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# 
# Top level modules:
# 	timing
vsim -voptargs=+acc work.timing
# vsim -voptargs=+acc work.timing 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading work.timing(fast)
# Loading work.decoder(fast)
add wave -position anchor  \
sim:/timing/adr \
sim:/timing/data_in \
sim:/timing/read \
sim:/timing/enable \
sim:/timing/clk \
sim:/timing/BL \
sim:/timing/BLB \
sim:/timing/WL \
sim:/timing/clk_en
force -freeze sim:/timing/read 1 0
force -freeze sim:/timing/enable 1 0
force -freeze sim:/timing/clk 1 0, 0 {50 ns} -r 100
run
run
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# 
# Top level modules:
# 	timing
vsim -voptargs=+acc work.timing
# vsim -voptargs=+acc work.timing 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading work.timing(fast)
# Loading work.decoder(fast)
add wave -position anchor  \
sim:/timing/adr \
sim:/timing/data_in \
sim:/timing/read \
sim:/timing/enable \
sim:/timing/clk \
sim:/timing/BL \
sim:/timing/BLB \
sim:/timing/WL \
sim:/timing/clk_en
force -freeze sim:/timing/read 1 0
force -freeze sim:/timing/enable 1 0
force -freeze sim:/timing/clk 1 0, 0 {50 ns} -r 100
run
run
run
force -freeze sim:/timing/data_in 1010101010101010 0
force -freeze sim:/timing/adr 1010 0
run
force -freeze sim:/timing/read 0 0
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v(29): near "end": syntax error, unexpected end, expecting ';'
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# 
# Top level modules:
# 	timing
vsim -voptargs=+acc work.timing
# vsim -voptargs=+acc work.timing 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading work.timing(fast)
# Loading work.decoder(fast)
add wave  \
sim:/timing/adr \
sim:/timing/data_in \
sim:/timing/read \
sim:/timing/enable \
sim:/timing/clk \
sim:/timing/BL \
sim:/timing/BLB \
sim:/timing/data_out \
sim:/timing/WL \
sim:/timing/clk_en
force -freeze sim:/timing/adr 1010 0
force -freeze sim:/timing/data_in 1010101010101010 0
force -freeze sim:/timing/read 1 0
force -freeze sim:/timing/enable 1 0
force -freeze sim:/timing/clk 1 0, 0 {50 ns} -r 100
run
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing
# 
# Top level modules:
# 	timing
vsim -voptargs=+acc work.timing
# vsim -voptargs=+acc work.timing 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading work.timing(fast)
# Loading work.decoder(fast)
add wave -position anchor  \
sim:/timing/adr \
sim:/timing/data_in \
sim:/timing/read \
sim:/timing/enable \
sim:/timing/clk \
sim:/timing/BL \
sim:/timing/BLB \
sim:/timing/data_out \
sim:/timing/WL \
sim:/timing/clk_en
force -freeze sim:/timing/adr 1111 0
force -freeze sim:/timing/data_in 1010101010101010 0
force -freeze sim:/timing/read 1 0
force -freeze sim:/timing/enable 1 0
force -freeze sim:/timing/clk 1 0, 0 {50 ns} -r 100
run
run
run
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v(13): Register is illegal in left-hand side of continuous assignment
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v(14): Register is illegal in left-hand side of continuous assignment
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# 
# Top level modules:
# 	timing2
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# 
# Top level modules:
# 	timing2
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# 
# Top level modules:
# 	timing2
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# 
# Top level modules:
# 	timing2
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# 
# Top level modules:
# 	timing2
vsim -voptargs=+acc work.timing2
# vsim -voptargs=+acc work.timing2 
# ** Note: (vsim-3812) Design is being optimized...
# Loading work.timing2(fast)
# Loading work.decoder(fast)
add wave -position anchor  \
sim:/timing2/adr \
sim:/timing2/data_in \
sim:/timing2/read \
sim:/timing2/enable \
sim:/timing2/clk \
sim:/timing2/BL \
sim:/timing2/BLB \
sim:/timing2/WL \
sim:/timing2/clk_en
noforce sim:/timing2/adr
force -freeze sim:/timing2/adr 1010 0
force -freeze sim:/timing2/data_in 1010101010101010 0
force -freeze sim:/timing2/read 0 0
force -freeze sim:/timing2/enable 0 0
force -freeze sim:/timing2/clk 1 0, 0 {50 ns} -r 100
run
run
force -freeze sim:/timing2/enable 1 0
run
force -freeze sim:/timing2/data_in 1010101010101011 0
run
force -freeze sim:/timing2/read 1 0
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v(14): (vlog-2730) Undefined variable: 'cenable'.
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# 
# Top level modules:
# 	timing2
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# 
# Top level modules:
# 	timing2
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# 
# Top level modules:
# 	timing2
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# 
# Top level modules:
# 	timing2
vsim -voptargs=+acc work.timing2
# vsim -voptargs=+acc work.timing2 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading work.timing2(fast)
# Loading work.decoder(fast)
add wave  \
sim:/timing2/adr \
sim:/timing2/data_in \
sim:/timing2/read \
sim:/timing2/enable \
sim:/timing2/clk \
sim:/timing2/BL \
sim:/timing2/BLB \
sim:/timing2/WL \
sim:/timing2/clk_en
force -freeze sim:/timing2/adr 1010 0
force -freeze sim:/timing2/data_in 1010101010101010 0
force -freeze sim:/timing2/read 1 0
force -freeze sim:/timing2/enable 0 0
force -freeze sim:/timing2/clk 1 0, 0 {50 ns} -r 100
run
run
force -freeze sim:/timing2/enable 1 0
run
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# 
# Top level modules:
# 	timing2
vsim -voptargs=+acc work.timing2
# vsim -voptargs=+acc work.timing2 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading work.timing2(fast)
# Loading work.decoder(fast)
add wave -position anchor  \
sim:/timing2/adr \
sim:/timing2/data_in \
sim:/timing2/read \
sim:/timing2/enable \
sim:/timing2/clk \
sim:/timing2/BL \
sim:/timing2/BLB \
sim:/timing2/WL \
sim:/timing2/clk_en
force -freeze sim:/timing2/adr 1010 0
force -freeze sim:/timing2/data_in 1010101010101010 0
force -freeze sim:/timing2/read 1 0
force -freeze sim:/timing2/enable 0 0
force -freeze sim:/timing2/clk 1 0, 0 {50 ns} -r 100
run
run
force -freeze sim:/timing2/enable 1 0
run
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# ** Error: /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v(11): near "wire": syntax error, unexpected wire
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# 
# Top level modules:
# 	timing2
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# 
# Top level modules:
# 	timing2
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# 
# Top level modules:
# 	timing2
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# 
# Top level modules:
# 	timing2
vlog -reportprogress 300 -work work /net/plato.ee.Virginia.EDU/users/jmb9zw/synopsys/syn_tut/dc/source/timing2.v
# Model Technology ModelSim SE vlog 10.1 Compiler 2011.12 Dec  5 2011
# -- Compiling module timing2
# 
# Top level modules:
# 	timing2
force -freeze sim:/timing2/read 0 0
run
# Causality operation skipped due to absense of debug database file
vsim -voptargs=+acc work.timing2
# vsim -voptargs=+acc work.timing2 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading work.timing2(fast)
# Loading work.decoder(fast)
add wave -position anchor  \
sim:/timing2/adr \
sim:/timing2/data_in \
sim:/timing2/read \
sim:/timing2/enable \
sim:/timing2/clk \
sim:/timing2/BL \
sim:/timing2/BLB \
sim:/timing2/WL \
sim:/timing2/clk_en
force -freeze sim:/timing2/adr 1010 0
force -freeze sim:/timing2/data_in 1100110011001100 0
force -freeze sim:/timing2/read 1 0
force -freeze sim:/timing2/enable 0 0
force -freeze sim:/timing2/clk 0 0, 1 {50 ns} -r 100
run
run
force -freeze sim:/timing2/enable 1 0
run
force -freeze sim:/timing2/read 0 0
run
